1. Field of the Invention
The present invention relates to a data processing system, and more specifically a data processing system capable of avoiding collision between read data and write data.
2. Description of Related Art
After a data processing system has read data from a memory or an input/output device through a data bus, if the data processing system starts a write cycle so as to output write data to the data bus, a collision occurs on the data bus between the read data outputted from the memory or the input/output device and the write data outputted from the data processing system, because a turn-off ready time of the memory or the input/output device is large.
In the prior art, in order to avoid this collision of data, a bi-directional buffer has been provided on the data bus between the data processing system and the memory or the input/output device, for the purpose of controlling the direction of the data bus (this will be called a "first prior art" hereinafter).
In addition, Japanese Utility Model Application Laid-open Publication No. Heisei 3-037544 has proposed to provide a control means receiving a device selection signal and a read/write signal generated by the data processing system, so as to generate a halt signal (data processor wait signal) to the data processing system, so that a halt condition is inserted after completion of the read cycle, whereby the data collision as mentioned above can be avoided (this will be called a "second prior art" hereinafter).
Now, the "first prior art" will be described with reference to the block diagram of FIG. 1 and the timing chart of FIG. 2.
A data processing system, generally designated by Reference Numeral 503 in FIG. 1, comprises a bus interface 603 and a clock generator 3 for supplying a clock signal 4 to the bus interface 603. The data processing system 503 is coupled through an address bus 1 to a memory 500, and also through a data processor side data bus 11 to a bi-directional buffer 630, which is also coupled through a memory side data bus 12 to the memory 500. In addition, the data processing system 503 is configured to supply a read strobe signal 2 to the bi-directional buffer 630 and the memory 500, and also to supply a write strobe signal 22 to the memory 500.
The bus interface 603 of the data processing system 503 includes a write buffer 5, a write data output signal generating circuit 703 and a write strobe signal generating circuit 711. The write buffer 5 is configured to output write data to the data processor side data bus 11 during a period in which a write data output signal 32 generated in the write data output signal generating circuit 703 is active. The write data output signal generating circuit 703 receives the clock signal 4 from the clock signal generator 3 and generates the write data output signal 32 to the write buffer 5. The write strobe signal generating circuit 711 receives the clock signal 4 from the clock signal generator 3 and generates the write strobe signal 22.
The bi-directional buffer 630 controls the direction of the data bus on the basis of the read strobe signal 2. When the read strobe signal 2 is active, the bi-directional buffer 630 outputs the date on the memory side data bus 12 to the data processor side data bus 11. When the read strobe signal 2 is inactive, the bidirectional buffer 630 outputs the data on the data processor side data bus 11 to the memory side data bus 12.
Now, operation of the "first prior art" shown in FIG. 1 will be explained with reference to FIG. 2.
When the data processing system 503 starts the read cycle, the bus interface 603 outputs the read address to the address bus 1, and activates the read strobe signal 2. With this, read data is outputted from the memory 500 to the memory side data bus 12. Since the read strobe signal 2 is active, the read data is outputted from the bi-directional buffer 630 to the data processor side data bus 11, and is sampled to the data processing system at a rising edge of the read strobe signal 2.
On the other hand, when the data processing system 503 starts the write cycle, the bus interface 603 outputs the write address to the address bus 1, and the write strobe signal generating circuit 711 activates the write strobe signal 22. In addition, the write data output signal generating circuit activates the write data output signal 32, and the write buffer 5 outputs the write data to the data processor side data bus 11 for a period in which the write data output signal 32 is active. Since the read strobe signal 2 is inactive, the write data is outputted through the bi-directional buffer 630 to the memory side data bus 12, and is written into the memory at a rising edge of the write strobe signal 22.
The externally provided bi-directional buffer 630 is ordinarily constituted of a TTL circuit, and a turn-off ready time T1 of the externally provided bi-directional buffer 630 is shorter than a turn-off ready time T2 of the memory 500, as shown in FIG. 2. Therefore, it is possible to avoid the collision of data on the data processor side data bus 11. In addition, the write data output signal 32 and the write strobe signal 22 are outputted at substantially the same timing, and it is not possible to change the output timing of these signals.
In the "first prior art" as mentioned above, however, the collision of data occurs on the memory side data bus (in the period T2 in FIG. 2). In addition, the extra bi-directional buffer 630 is required.
On the other hand, the "second prior art" is disadvantageous, since the halt condition is inserted after completion of the read cycle, and thus a next cycle is delayed by a time period necessary for the halt condition.